1. Field of the Invention
The present invention relates to a display device using the method of intraframe time-division multiplexing which reduces the gray-scale disturbance occurring when, for example, such a display devices as one using a gas discharge panel is used to display pictures, and to a method therefor.
2. Description of the Related Art
In recent years, as display devices have become larger, there has arisen a demand for thin display devices and a variety of thin display devices has been proposed.
Of these, there are display panels which have two stable operating states and, in order to perform multiple-level gray-scale display with such display panels, the method of intraframe time-division multiplexing is used.
However, when this method is used to display a picture, disturbance of the gray-scales causes a drop in picture quality, and this problem must be solved to achieve an improvement in picture quality.
In the past, intraframe time-division multiplexing was a method used for performing gray-scale display in display panels that had only two stable operating states, on and off.
In the past such devices as gas discharge display panels, liquid-crystal display panels, and fluorescent discharge display panels were used as display devices employing the method of intraframe time-division multiplexing, and an actual example of such a gas discharge display panel would be, for example, a plasma display device.
These intraframe time-division multiplexing type display devices have become small in depth and now have large areas, which has led to a sudden broadening of their applications and growth in production levels.
An actual example of a gas discharge panel which uses the intraframe time-division multiplexing method is described in the form of a plasma display device for the purpose of explaining the prior art in methods of performing gray-scale display.
Such flat plasma display devices generally use the electrical charge accumulated between electrodes to cause the emission of light, and this general display principle and the related construction and operation are described briefly below.
Well-known plasma display devices in the past (AC type PDP) include a two-electrode type in which selection discharge (address discharge) and sustained discharge are performed by two electrodes, and a three-electrode type in which a third electrode is used to perform address discharge.
Specifically, FIG. 5 shows a simplified top plan view an example of the configuration of a three-electrode type plasma display device of the prior art, and FIG. 6 shows a simplified cross-sectional view of one of the discharge cells 10 formed in the plasma display device of FIG. 5.
This plasma display device, as can be seen in FIG. 5 and FIG. 6, is formed from two glass substrates 12 and 13. The 1st glass substrate 13 is provided with 1st electrodes (X electrodes) 14 and 2nd electrodes (Y electrodes) 15 which act as sustaining electrodes, which are disposed so as to be mutually parallel, these electrodes being covered by an electrolytic layer 18.
In addition, a protective film of MgO (magnesium oxide) is formed, as covering film 21, on the discharge surface represented by the electrolytic layer 18.
On the surface of the 2nd glass substrate 12, which is opposite the above-noted 1st glass substrate 13, is formed a 3rd electrode 16, which acts as an address electrode, and which disposed so as to be perpendicularly to the above-noted sustaining electrodes 14 and 15.
On top of the address electrodes 16 a phosphor 19 having a color emitting character of red, green, or blue is formed, this being located in the discharge space 20 which is established by the wall 17 which is formed in the same plane in which is located the address electrodes of the above-noted 2nd glass substrate 12.
That is, each of the discharge cells 10 of this plasma display device is separated by a wall (barrier).
In the actual example of a plasma display device noted above, the 1st electrodes (X electrodes) 14 and 2nd electrodes (Y electrode) 15 are disposed so as to be mutually parallel, each forming a pair, with the 2nd electrodes (Y electrodes) 15 being each separately driven by separate Y electrode drive circuits 4-1 to 4-n which are connected to a common Y electrode drive circuit 3, and with the 1st electrodes (X electrodes) 14 forming a common electrode and being driven by a single drive circuit 5.
Perpendicularly crossing the X electrodes 14 and the Y electrodes 15 are the address electrodes 16-1 to 16-m, these address electrodes 16-1 to 16-m being connected to an appropriate address drive circuit 6.
In this flat display device, each line of the address electrodes 16 is connected to the address driver 6, the address driver 6 applying the address pulses to each of the address electrodes.
The Y electrodes 15 are each connected separately to the Y scan drivers 4-1 to 4-n.
The address scan drivers 4-1 to 4-n are further connected to the common Y electrode driver 3, with address discharge pulses being generated by the scan drivers 4-1 to 4-n, and with sustained discharge pulses, etc. being generated by the common Y driver 33 shown in FIG. 7, these passing through the Y scan drivers 4-1 to 4-n and being applied to the Y electrodes 15.
The X electrodes 14 are commonly connected and driven across the entire display line of the panel of this flat display device.
That is, the common X electrode driver 5 (32 in FIG. 7) generates write pulses and sustained pulses, these being applied in parallel to each of the X electrodes 14.
These drive circuits are controlled by a control circuit (not shown in the drawings), this control circuit being in turn controlled by synchronization signals and display data signals applied from outside the device.
As described above, in a display panel 1 of a prior art flat display device, the above-noted sustained electrodes 10 are located so as to form a matrix of m in the horizontal direction and n in the vertical direction, with the Y side scan driver circuit 4-1 driving the Y electrodes that are connected to sustained discharge cells 10 that are uppermost in the vertical direction and arranged in a row of m cells, and in the same manner each of the Y side scan drive circuits 4-2 to 4-n separately drive the Y electrodes which are the scan display lines corresponding to each of them.
The X electrode drive circuit 5 drives the X electrodes, which run in parallel to the Y electrodes, but which form a common electrode and are thus driven in common by a single X electrode driver circuit 5.
FIG. 7 is a simplified block diagram which shows the peripheral circuitry which drives the plasma display shown in FIG. 5 and FIG. 6, in which address electrodes 16 are each connected separately to address driver 31, this address driver 31 applying address pulses to each of the address electrodes at the time of address discharge.
The Y electrodes 15 are connected separately to a Y scan driver 34.
This Y scan driver 34 is further connected to a common Y driver 33, with pulses generated by the scan driver 34 at the time of address discharge, and sustained discharge pulses, etc. generated by the common Y driver 33, passing through the Y scan driver 34 to the Y electrodes 15.
The X electrodes 14 are connected in common across the entire display line of the panel of this flat display device.
That is, the common X electrode driver 32 shown in FIG. 7 (5 in FIG. 5) generates such pulses as write pulses and sustained pulses, these pulses being applied in parallel and simultaneously to each of the Y electrodes 15.
The driver circuits are controlled by a control circuit, this control circuit being controlled by synchronization signals and data signals input from outside the device.
Specifically, as can be seen from FIG. 7, the address driver 31 is connected to the display data control section 36 provided in the control circuit 35, this display data control section 36 receiving externally applied inputs, such as display data signals (R7 to R0, G7 to G0, B7 to B0) and a dot clock signal (CLOCK), via a display data pre-processor section 43 and storing them into, for example, a frame memory 71, and the address driver outputs the output data within a single frame from the frame memory 71, for example, which is synchronized to the address timing of the address electrodes to be selected.
The Y scan driver 34 is connected to the scan driver control section 39 of the panel drive control circuit section 38 provided in the control circuit 35, the Y scan driver 34 being driven in response to an externally input vertical synchronization signal V.sub.SYNC which is the signal indicating the start of one frame (one field), a number of Y electrodes 15 in the flat display device 1 being selected in sequence to display one frame of the image.
In FIG. 7, the Y-DATA which is output from the scan driver control section 39 is scanning data for the purpose of setting one bit of the Y scan driver on at a time.
Both the common X electrode driver 32 and the common Y electrode driver 33 in this example are connected to the common driver control section 40 provided in the control circuit 35, these acting to reverse the polarity of the voltage applied to the voltage alternately applied to the X electrodes 14 and the Y electrodes 15 while driving them both, thereby achieving the sustained discharge noted above.
Within the above-noted display data control section 36 a frame memory control circuit 42 is additionally provided, this frame memory control circuit 42 being controlled by the PDP timing generation circuit 74 provided in the panel driver control circuit section 38.
FIG. 8 shows the waveforms associated with the previous method of driving the plasma display device PDP shown in FIG. 5 and FIG. 6, this drawing showing the operating waveforms in one sub-frame of the several sub-frames (the six sub-frames SF1 to SF6 in FIG. 8) which make up a frame in what is known as the time-separated address/sustained type of write addressing.
In this example, a single sub-frame SF is composed of at least the three period, such as reset period S1, addressing period S2, and sustained discharge period S3, and in this reset period S1, as described above, immediately before displaying the image for a new sub-frame, to erase the display (lighted) states for each sub-frame of the previous frame, all the Y electrodes are set to 0 V level and, simultaneously, the write pulse (WP) consisting of the voltage V.sub.W is applied to the X electrodes.
After that, when the Y electrode voltage becomes Vs and the X electrode voltage becomes 0 V, sustained discharge is performed on all cells, this executing writing processing over the entire surface, an erase pulse (EP) being applied to X electrodes 14 to first erase the information stored at each of the cells 10.
This period is called the reset period S1.
What happens is that, in the reset period S1 of the example being described, all Y electrodes are set to a 0 V level and, simultaneously, a write pulse consisting of a voltage V.sub.W is applied to the X electrodes, thereby causing discharge at all cells of all display lines. Following that, the potential at the Y electrodes becomes the level Vs and simultaneously the potential at the X electrodes become the level 0 V, so that sustained discharge is performed on all cells. In addition, after that, with the potential on the Y electrodes at the 0 V level, the erase pulse (EP), which is a potential of V.sub.E is applied to the X electrodes, this causing an erase discharge between the X and Y electrodes, which reduces the wall electrical charge (neutralizes part of the wall electrical charge).
This reset period S1 has the effect of setting all cells to the same state, regardless of the states of the cells in the previous sub-frame and, as its object, leaves a wall electrical charge advantageous for address discharge, so that discharge will not start even if a sustained pulse is applied.
Next, in this actual example, following this reset period S1, there is provided an addressing period S2, during which, in response to display data, an address discharge is performed in line sequence for the purpose of setting cells on and off.
First, along with a scan pulse SCP, at a 0 V level, being applied to the Y electrodes, addressing pulse ADP, at a voltage Va, is selectively applied to the address electrodes of those cells which are to be sustained discharged, that is, which are to be lighted, so that write discharge is performed on the cells to be lighted. By doing this, a small discharge that cannot be directly perceived occurs between these address electrodes and the selected Y electrodes, and writing (addressing) of the display line is completed when the prescribed amount of electrical charge is accumulated in the corresponding cells 10.
Thereafter, the same type of operations are performed for the other display lines, so that new display data is written to all the display lines.
After that, when the sustained discharge period S3 is entered, a sustained pulse of a voltage Vs is alternately applied to the Y electrodes and X electrodes to perform sustained discharge, so that one sub-frame of the image is displayed.
In this time-separated address/sustained type of write addressing, the length of the sustained discharge period, that is, the number of sustained pulses, establishes the intensity of the displayed image.
The intensity of display pixels of this displayed image is dependent upon the number of sustained discharges in the sustained discharge period S3, which is based on the sub-frame setting conditions selected in each sub-frame, or stated differently, it is dependent upon the length of the sustained discharge period.
Basically, the larger the number of sustained discharges during this sustained discharge period S3 is, the higher will be the intensity, and the smaller the number of sustained discharges during this sustained discharge period S3 is, the lower will be the intensity.
In the example of the sub-frame of FIG. 8, in the case in which the sub-frame SF1 is used to execute the sustained discharge operation, the displayed image is the darkest. In contrast to this, in the case in which the sub-frame SF6 is used to execute the sustained discharge operation, the display is the brightest.
If these sub-frames are combined appropriately, it is possible to produce a gray-scale display with a large number of levels. In the example shown in FIG. 8, as shown in FIG. 10, there is a method of combining these to enable a display of 64 gray-scale levels.
Therefore, the adjustment of the gray-scale display levels of intensity is done by appropriately selecting sub-frame patterns from a number of sub-frame patterns set to given weights in terms of number of sustained discharges for each sub-frame, sustained discharge being executed at each of the sub-frames, the overall combined result being the gray-scale display level of a given single frame.
Although the rest period S1 and addressing period S2 of each of sub-frame SF1 to SF6 in FIG. 8 are the same length in time, the time length of the sustained discharge periods S3 are different for each of the sub-frames. For example, the number of sustained discharges from sub-frame SF1 to sub-frame SF6 is set to run in the series 1:2:4:8:16:32, and it is possible to set the number of sustained discharges in a given single sub-frame as desired, by using an appropriate address to select one or a number of the sub-frames SF1 to SF6.
That is, in the example shown, it is possible to display the intensity as gray-scale display levels 0 through 63, by using selected combinations of the sub-frames.
Furthermore, in the example of FIG. 8, there are six types of sub-frames. The present invention, however, is not limited to six sub-fields, it being possible to make use of any combination of either eight types or four types.
In this manner, the time-separated address/sustained method of write addressing makes use of the memory function of an AC type PDP plasma display device, and is even to this day an advantageous method of efficiently making use of time in achieving a gray-scale display.
FIG. 9 shows the display data control section 35 and the timing generation section 74 of the plasma display (PDP). The display data control section 35 receives the display data of the CRT-interface signals and temporarily stores this into the frame memory section 71.
This is done for the purpose of dividing the gray-scale data of the display data of the CRT-interface signals in the time-axis direction. To divide it in the time-axis direction, and to prevent contention between the input of the input data to and the output from the output data of the display data control section 35 from the frame memory section 71, this frame memory is formed from two frame memories, which alternately perform write and read out of data for each frame.
That is, when frame memory A44 is performing a writing operation, frame memory B45 is performing a readout operation.
In the drawing, 46 and 47 are line switchers, the switching direction of which differs depending upon the operational states of the frame memories.
The display data pre-processing section 43 is a circuit which performs pre-processing of the data to be written into the frame memory 71 so as to achieve efficient readout of address driver data (A-DATA) from frame memory section 71.
The frame memory control circuit section 42 receives control signals from the PDP timing generation circuit section 74, and generates the write/read address signals for the frame memory section 71.
The switching of the frame memory section 71 write/read address signals is performed by selectors 48 and 49.
The switching of selectors 48 and 49 is executed by the FTOG signal (a signal whose logic state inverts every frame).
The write address MWA (multiplex write address) is derived by multiplexing, by multiplexer MUX 51, the write ROW address signal (RWA) generated by the write ROW address generation circuit 53 and the write COLUMN address signal (CWA) generated by the write COLUMN address generation circuit 55.
The write ROW address generation circuit 53 is reset by FLCR (frame clear) signal, and the address is incremented by the DWST (data write start) signal.
The FLCR (frame clear) signal is output at the vertical synchronization signal V.sub.SYNC, and the DWST (data write start) signal is output each time the BLANK signal is input.
The write COLUMN address generation circuit is reset by the DWST signal and is incremented at each dot clock.
The read address signal MRA (multiplex read address) is derived by the multiplexer MUX 50 multiplexing the read ROW address (RRA) signal generated by the read ROW address generation circuit 52, the lower order read COLUMN address (RCA0) generated by the read COLUMN address generation circuit 54, and the output of the sub-frame counter within the PDP timing generation circuit section 74 (RCA1: upper order read COLUMN address).
The read ROW address generation circuit 52 is reset by the SFCLR (sub-frame clear) signal, and incremented by the ADTT (address data transmission timing) signal which is output for each panel scan line.
The read COLUMN address generation circuit 54 is reset by the ADTT signal and incremented in synchronization with the address data transmission clock (A-CLOCK).
The sub-frame display data to be read is determined by the RCA1 signal.
The PDP timing generation circuit 74 is formed from the interface circuit section 70, the sub-frame forming means 73, and the sub-frame counter 72.
The interface circuit section 70 has the unit control signals (V.sub.SYNC, H.sub.SYNC, BLSNK, and CLOCK) input to it, and generates the FCLR, FTOG, and DWST signals.
The sub-frame counter 72 is reset by the FCLR signal and incremented by the SFCLR signal.
When the FCLR signal is input, the drive sequence within the sub-frame, that is, the sequence S1, S2, S3 is executed, and when this sequence is completed, the sub-frame forming means 73 outputs the SFCLR signal.
The generation of the SFCLR signal causes the sub-frame forming means 73 to start the sub-frame internal drive sequence again.
These operations are repeated until the prescribed number of sub-frames within the frame are executed.
The drive sequence S3 within the sub-frame, that is, the sustained discharge pulse selection, is determined by the value of the output RCA1 of the sub-frame counter.
In the above-described plasma display device, as described above, a single frame is composed of a number (N) of sub-frame having mutually different intensities, these sub-frames being appropriately combined to obtain a display with 2.sup.N gray-scale display levels. However, in the past, the selection of the number of sub-frames and sequence for driving each of the sub-frame to perform sustained discharge is limited to a predetermined fixed sequence, this sequence being uniform along the time axis.
In such a case, when displaying a moving image, or when performing analog-to-digital conversion for display of an analog signal source such as a video signal, a particular gray-scale level often occurs repeatedly.
When this condition occurs at, for example, a point at which there is a bit carry (for example between 127 and 128, 63 and 64, 31 and 32, or 15 and 16), with prior art, even if the frame frequency is one at which flicker does not normally occur (for example, 60 Hz), a low-frequency (display drive) component (30 Hz) occurs, this appearing as a partial flickering, causing a significant reduction in image quality.
To explain this problem more specifically, consider, as in the case described above, the case in which, as shown in FIG. 8 there are six sub-frames from SF1 to SF6, and wherein the intensity ratios between these sub-frames, that is, the sustained discharge period ratios between the sub-frames is set to be as follows.
SF1:SF2:SF3:SF4:SF5:SF6=1:2:4:8:16:32
In this case, the 31st gray-scale level is the condition in which sustained discharge is done so that all the sub-frames from SF1 to SF5 are lighted simultaneously, and the 32nd gray-scale level is the condition in which sustained discharge is done so that only sub-frame SF6 is lighted.
In this case, if the display data fluctuates between gray-scale level 31 and gray-scale level 32, as shown in FIG. 11, the lighted states in each sub-frame are as indicated by the circles and Xs (circle indicating on and X indicating off), and as a result, this is equivalent of having the 63rd gray-scale level (that is, the condition in which all the sub-frames from SF1 to SF6 are on simultaneously) turn on and off every alternately every frame, so that for two adjacent frames a low-frequency component is formed, this generating a prominent flicker.
This relationship would generate the same condition if, for example, the display data fluctuated between the 15th and 16th gray-scale levels as shown in FIG. 11 a pseudo-flickering condition being generated at the 31st gray-scale level at a low frequency corresponding to the 31st gray-scale level.
Because this phenomenon tends to occur more, the higher the intensity level is, a method has been proposed as in, for example, Japanese Unexamined Patent Publication No. 3-145691, of reducing this phenomenon by locating sub-frames having relatively higher intensity, as much as possible near the center of a single frame. The example given being that of the position-changing method, in which the sub-frame with the highest intensity is located in the center of the frame, with successively lower 2nd highest and 3rd highest intensity sub-frames located to either side of that sub-frame. However, even this method fails to achieve a sufficient effect.
In the gray-scale display of FIG. 8, it is known that, with the intensity being approximately the same, in the case in which there is no overlap of "on" sub-frames, or little overlap in terms of time, that is, in the case in which gray-scale levels in which the sub-frames having overlapping of low intensity weights are laid positioned next to one another, flicker occurs in their boundary areas, this reducing the quality of the display.
The higher the intensity is, the more prevalent this phenomenon becomes. This phenomenon is observed to be prominent in such displays as gray-scale displays.
The principle behind the problem involved is almost the same as described for the previous problem. In the case of this phenomenon, however, because the eyeball vibrates very minutely, the image projected on to the retina of the eye vibrates, there being a characteristic repetition generated at the retina between specific gray-scale levels, this appearing as a 30-Hz flicker.
With regard to this, it has been reported (in Japanese Unexamined Patent Publication No. 4-127194) that an improvement is produced by dividing the emitted light of the uppermost order sub-frame into two and positioning it so that the light-emitting period of sub-frames with high intensity is double the frame frequency.
However, sub-frames with low intensity still produce flicker as before.
The above-noted two problems are phenomena that occur with static images.
In the case of moving images, for a reason completely different from the above-noted problems, there is an additional disturbance in the gray-scale levels, as made clear from experiments done by the inventors of the present invention.
This gray-scale level disturbance specifically manifests itself as either bright lines or dark lines appearing in specific gray-scale levels when a gray-scale display is scrolled in the intensity gradient direction.
The intensity of the bright lines and the gray-scale level at which they appear depend upon the scroll direction and on the sub-frame arrangement.
As a more specific example, when the flesh-colored part of a persons cheek, for example, moves, a false contour in reddish purple or green is generated at the flesh-colored part (this phenomenon being referred to hereafter as false colored contour), this reducing the quality of the moving image display.
The mechanism by which the gray-scale level disturbance occurs in a moving image is described below, for the case in which there are six sub-frames in one frame, with reference being made to FIG. 13 through FIG. 15.
In this case, however, the arrangement of the sub-frames from the start is SF6, SF5, SF4, . . . , SF1.
When a display of the sub-frame SF6 (uppermost order sub-frame SF) of one vertical blue line is scrolled from the right to the left, if for example there is movement of one pixel in one frame in the display, it will appear as if this has moved to another sub-pixel that is not on, and a smooth motion will be observed.
This smooth motion will be observed even if the moving pixel in the frame is quite large.
In the field of psychology, this phenomenon is known as apparent movement or b movement.
Next, if a display of the sub-frames SF6 and SF5 of one vertical blue line is turned on and scrolled in the same manner as described above, as shown in FIG. 13, it is observed that the color of each sub-frame will be displayed spatially separated. FIG. 13 shows the appearance of the colored cells when displaying the blue SF6 and SF5 sub-frames and scrolling one dot from the right to the left at 1 Vsync, and while this is simply shown as the coloring of the sub-frame SF6 over the blue sub-pixel (B), it will appear, for the same reason as noted above, as if it was moving over sub-pixels of other colors as well.
This is because after the sub-frame SF6 is turned on the sub-frame SF5 emits color after an approximately 2 ms display data write period, the above-noted apparent movement phenomenon causing the appearance to the human eye of the sub-frame SF6 moving in the scrolling direction, with the color emission of sub-frame SF5 appearing to chase the sub-frame SF6.
In the same manner, if all the sub-frames within one frame are turned on and this is scrolled, as shown in FIG. 14, the color emissions of blue sub-frames SF6 to SF1 appear to be displayed spatially separated. FIG. 14 shows the appearance of the color emitting cells when displaying the blue sub-frames SF6 to SF1 and scrolling one dot from right to left at 1 Vsync.
In addition, FIG. 15 shows the appearance of the color emitting cells resulting from displaying the blue sub-frames SF6 to SF1 and scrolling two dots from the right to the left at 1 Vsync, that is, the observed results in the case of moving one frame by 2 pixels.
In this case, what is actually causing emitted colors is the doubling or the spacing of the sub-pixels so that the speed of the apparent movement is faster to the extent that the movement distance increases.
Therefore, if sub-frame SF5 emits color approximately 2 ms after the sub-frame SF6 emits its color, the color-emitting part of the sub-frame SF6 is more distant, so that there is the appearance that there is more sub-frame spatial separation, that is, the appearance that the color-emitting spacing is widened.
The spatial widening of the sub-frames when apparent movement takes place was seen, from observations, to be approximately widened within a pixel which moves within one frame period.
Therefore, whereas a gray-scale value should be expressed as the result of turning the same pixel on and integrating the intensity of each sub-frame in the time direction, it was found that with a moving image it is not possible to express a gray-scale level as the sum of the intensities of each sub-frame within the frame, a gray-scale disturbance occurring for moving images.
In a display with no color (white display), this disturbance occurs as bright or dark lines, and in a display having color, it appears as a color other than the original color being generated.
FIGS. 32 and 33 are diagrams for explaining a mechanism of generating a gray-scale level disturbance during display of a dynamic image. Referring to the drawings, the mechanism of generating a gray-scale level disturbance will be described.
In FIGS. 32 and 33, the number of sub-frames within a frame is six. Blue, red, and green pixels are repeatedly displayed in that order during the sub-frames. The sub-frames are arranged in the sequence of sub-frames SF6, SF5, SF4, etc., and SF1 from the leading sub-frame.
When a display containing one blue vertical line produced by cells lit during sub-frame SF6 (highest level sub-frame SF) is scrolled from right to left, for example, when a display is shifted by one pixel per frame, and the blue vertical line appears to move over sub-pixels of other colors corresponding to unlit cells. A smooth motion is observed. The smooth motion is observed even when the number of pixels to be shifted per frame is considerably large. This phenomenon is referred to as a quasi-color pixel effect or beta movement in the field of psychology.
Next, when a display in which one blue vertical line produced by cells lit within sub-frames SF6 and SF5 is scrolled from right to left, as shown in FIG. 32, states of light emission or glow occurring during the sub-frames are seen spatially separately displayed. FIG. 32 shows how states of glow occurring during sub-frames SF6 and SF5 are seen when a display is scrolled by one dot from right to left synchronously with a signal Vsync. Glow occurring during sub-frame SF6 is exhibited as a blue sub-pixel (B). For the aforesaid reason, the sub-pixel is seen as if it were moving over other sub-pixels.
When a cell is lit during sub-frame SF6, if the cell is lit during sub-frame SF5 that lags behind sub-frame SF6 by approximately 2 msec. of a display data writing period, the glow occurring during sub-frame SF6 is seen to move in the scroll direction because of the aforesaid quasi-color pixel effect. Human eyes therefore discern the image as if the glow occurring during sub-frame SF5 were chasing the glow occurring during sub-frame SF6. The glow during sub-frame SF5 is seen as if it were the glow of a cell corresponding to an adjoining red sub-pixel (R). This results in great deterioration of color discernment.
Likewise, when a cell is lit during all sub-frames within one frame, if a display is scrolled, as shown in FIG. 33, the glow occurring during sub-frames SF6 to SF1 is seen spatially separated at the same one pixel. FIG. 33 is a diagram showing how the blue glow occurring during sub-frames SF6 to SF1 is seen when a display is scrolled from right to left by two dots synchronously with a signal Vsync. In this case, since a spacing by which a sub-pixel is seen separated is doubled, the speed of light seen moving because of the quasi-color pixel effect increases. If glow occurs during sub-frame SF5 within approximately 2 msec. after glow occurs during sub-frame SF6, therefore, the glow during sub-frame SF6 is seen having moved farther. The spatial separation occurring during sub-frames, that is, the spread of glow extends over sub-pixels over which a pixel is seen moving during one frame.
Fundamentally, the luminance levels associated with sub-frames during which one cell corresponding to a sub-pixel glows are integrated with respect to time, whereby a gray-scale level is expressed. In the case of a dynamic image, since the glow occurring during the sub-frames within one frame is seen spatially different, a gray-scale level cannot be expressed by the sum of the luminance levels associated with the sub-frames. Consequently, a gray-scale level disturbance occurs in a dynamic image.
In a colorless (white) display, the disturbance appears as a dark line or bright line. In a color display, the disturbance appears as a color different from an original color.
Furthermore, Japanese Unexamined Patent Publication No. 3-145691 has, as already mentioned, disclosed the method in which a sub-frame to which the largest weight is assigned is arranged in the center of one frame in an effort to reduce the occurrence of flicker. FIG. 34 shows a sequence of sub-frames, during which a cell is lit, based on the method disclosed in the Japanese Unexamined Patent Publication No. 3-145692 and employed when a gray-scale level varies between gray-scale levels 127 and 128 depending on a frame. According to the sequence shown in FIG. 34, sub-frames are arranged in the sequence of sub-frames SF1, SF3, SF5, SF7, SF8, SF6, SF4, and SF2 in an effort to suppress flicker. As apparent from the drawing, when sub-frames are arranged in the sequence of sub-frames SF1, SF3, SF5, SF7, SF8, SF6, SF4, and SF2, a glow cycle or an interval between sub-frames during which a cell is lit becomes shorter than that in the case shown in FIG. 9, that is, becomes equal to one frame. Consequently, no flicker appears.
As mentioned above, according to the method of rendering a gray-scale level in an AC type PDP display device shown in FIG. 34, flicker occurring with a high-order bit of value transition or a high-order bit making a transition from the value of a preceding bit to another value (when a gray-scale level is high) can surely be suppressed. However, there is a problem that flicker occurring with a low-order bit of value transition (when a lower gray-scale level is low) becomes more conspicuous. Referring to FIG. 35, a mechanism of bringing about the problem with a low-order bit of value transition will be described.
FIG. 35 shows the lit states during sub-frames within frames associated with lower gray-scale levels in contrast with FIG. 34.
In FIG. 35, the states of a cell lit with a low-order bit of value transition according to, for example, gray-scale level 1 (during sub-frame SF1) and gray-scale level 2 (during sub-frame SF2) alternately frame by frame are shown. As illustrated, a glow interval or the interval between sub-frames SF1 and SF2 within adjoining frames during which the cell is lit is so short that the cell is seen lit at gray-scale level 3 at intervals of a cycle that is double that of a frame. The lit state of the cell at gray-scale level 3 is discerned as flicker by human eyes. Thus, when a gray-scale level is low, flicker occurs with a low-order bit of value transition, for example, with a change of gray-scale levels according to which a cell glows alternately during sub-frames SF1 and SF2 within adjoining frames.